The present application relates to systems, devices and methods for maskless substrate material deposition, removal and modification using charged particle beams; and more particularly to directly and precisely manufacturing patterned substrates as defined in a design layout database using multiple, matched charged particle beams, with the assistance of gas and/or photon injection, and/or of gas and/or photon process control, metrology and endpoint detection, such that multiple different processes using multiple different chemistries can be performed independently and simultaneously in the same vacuum space.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
FIG. 2A shows an example of a wafer 200 being scanned by multiple charged particle beams 204 emitted by respective miniature electrostatically-deflected beam columns 206. Individual columns 206 are able to target a portion of the substrate surface 706, called herein a “writing area” 202, with their respectively emitted beams 204.
FIG. 2B shows an example of a wafer 200. Example die 208 size and column 206 center-to-center spacing 210 (column separation) are shown. A regular grid of columns 206 (schematically indicated in FIG. 2B via their center positions, represented here as plusses) can use different spacing 210 in different (generally, orthogonal) directions. Die 208 size and column separation 210 are not required to (and generally, will not) correspond. Column separation 210 generally corresponds to the “writing area” 202 of corresponding columns 206. A column's 206 “writing area” 202 is defined as the substrate area 202 targetable by a charged particle beam 204 emitted from the column 206, taking into account stage 404 movement.
The multiple column 206 array 402 comprises miniature (small enough to fit multiple columns 206 in an array 402) charged particle beam columns 206 arranged in a regular grid. For example, column 206 arrays with center-to-center column spacing 210 of 30 mm×30 mm have been implemented, though other column spacings 210 (e.g., 24 mm×33 mm) can also be used.
A stripe is the portion of the wafer 200 surface that a charged particle beam can target while the stage 404 is moving predominantly in a single direction, i.e., before the stage 404 moves laterally and switches predominant directions to give the beam access to a different stripe. A “frame” 710 is defined herein as the portion of the wafer 200 (or other substrate 704) surface that a beam 204 can target at a given time, corresponding to the main-field deflection area 710 at that time, as designated by the design layout database. A frame 710 is typically designated to be rectangular, for convenience (e.g., to tile the writing area 202); and smaller than the furthest extent to which the beam 204 can be deflected (e.g., to preserve beam 204 targeting accuracy).
“1-D” refers to 1-D gridded design rule. In a 1-D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1-D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool comprising an array of columns 206—for example, electrostatically-controlled miniature electron beam columns 206. A 1-D layout is separated in the design layout database into a “line pattern” and a “cut pattern”. The design layout database contains the information needed by lithography tools to pattern one or more layers on a substrate 704. A line pattern generally comprises an array of unidirectional lines. Cut patterns generally comprise line-cuts and holes.
Generally, line patterns are written by an optical lithography system, which can be followed by other process steps to increase the density of lines on the substrate 704. Cut patterns are written by a complementary (generally higher-resolution) process, such as electron beam lithography. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The combination of the line-forming process followed by line-cuts written with CEBL to pattern a substrate layer is called complementary lithography.
FIG. 2C shows an example of a prior art process for removing material from a substrate surface 706.
Typically, as shown in FIG. 2C, a design layout database is accessed 212 to designate where substrate surface 706 material should be removed (e.g., to form new pattern or repair previously-formed pattern). One or more optical masks are fabricated based on the design layout database 214 using a mask making tool 216. Fabrication of a set of optical masks for one microchip design typically takes weeks and costs millions of dollars at advanced process nodes.
A hard mask is blanket deposited on the substrate surface 706 in step 218 by a deposition tool 220, and a photoresist layer is blanket deposited on the substrate surface 706 in step 222 by a resist deposition tool 224.
“Blanket” deposition and etch generally refers to deposition and etch on the entire surface 706 of the substrate 704.
“Resist” refers herein to a class of materials used in substrate lithography. When a resist is deposited on a substrate 704 and exposed to an energy source corresponding to the type of resist (e.g., photons for a photoresist) in a chosen pattern, its chemical properties change such that when the resist is developed (in ways similar to developing a photographic film), a portion of the resist corresponding to a positive or negative image of the pattern (depending on the type of resist) will remain, allowing the pattern to be expressed in the material underlying the resist, e.g., using etch steps.
The photoresist is then exposed using the optical mask(s) 226 by an optical lithography tool 228. The exposed portion of the resist layer (as designated by the optical mask(s)) is removed 230 using a resist developing tool 232, and the resulting patterned resist layer is inspected for defects and process control metrology (After Develop Inspection (ADI) and metrology) 234 by an inspection tool 236. Yield-reducing errors can be reduced by other tools, adding additional steps, and potentially additional defects.
The hard mask is then blanket etched through the pattern expressed in the resist layer 238, by an etch tool 240, to express (substantially) the same pattern in the hard mask layer. The resist layer is then removed 242 by a resist removal tool 244, and the material underlying the hard mask is blanket etched through the pattern expressed in the hard mask 246, using an etch tool 248 (e.g., a reactive-ion etch or ion milling tool, generally the same type of tool as etch tool 240), to express (substantially) the same pattern in the underlying material.
FIG. 2D shows an example of a prior art process for depositing material onto a substrate surface 706.
Typically, as shown in FIG. 2D, a design layout database is used to designate 212 where on a substrate surface 706 material should be deposited (e.g., to form new pattern or repair previously-formed pattern). One or more optical masks are fabricated based on the design layout database 214 using a mask making tool 216.
A pattern material is blanket deposited 250 and a hard mask is blanket deposited 218 on the substrate surface by a deposition tool 220. A photoresist layer is blanket deposited on the substrate surface 706 in step 222 by a resist deposition tool 224. The photoresist is then exposed using the optical mask(s) 226 by an optical lithography tool 228. The exposed portion of the resist layer (as designated by the optical mask(s)) is removed 230 using a resist developing tool 232, and the resulting patterned resist layer is inspected for defects and process control metrology (After Develop Inspection (ADI) and metrology) 234 by an inspection tool 236.
The hard mask is then blanket etched through the pattern expressed in the resist layer 238 by an etch tool 240 to express (substantially) the same pattern in the hard mask layer. The resist layer is then removed 242 by a resist removal tool 244, and the material underlying the hard mask is blanket etched through the pattern expressed in the hard mask 246, using an etch tool 248, to express (substantially) the same pattern in the underlying (pattern) material (added in step 250). The hard mask is then removed 252 using a hard mask removal tool 254.
FIG. 2E shows an example of a prior art process for modifying material on (or in) a substrate 704 using ion implantation.
Typically, as shown in FIG. 2C, a design layout database is used to designate 212 where on a substrate 704 material should be modified (e.g., to form transistor active areas through ion implantation). One or more optical masks are fabricated based on the design layout database 214 using a mask making tool 216.
A photoresist layer is blanket deposited on the substrate surface 706 in step 222 by a resist deposition tool 224. The photoresist is then exposed using the optical mask(s) 226 by an optical lithography tool 228. The exposed portion of the resist layer (as designated by the optical mask(s)) is removed 230 using a resist developing tool 232, and the resulting patterned resist layer is inspected for defects and process control metrology (After Develop Inspection (ADI) and metrology) 234 by an inspection tool 236.
The substrate surface 706 is then blanket modified 256 (using ion implantation), through the pattern expressed in the resist layer by steps 226 and 230, using an ion implantation tool 258 to express (substantially) the same pattern in the underlying material. The resist layer is then removed 242 by a resist removal tool 244.
Typically, functional substrate devices are built using a combination of material removal, deposition and modification processes.
FIG. 2F shows an example of a prior art process for etching differentiated-profile structures that are then uniformly filled. Etch structures can be manufactured to one depth using a mask set in an iteration of the steps shown in FIG. 2C; additional etch structures can be manufactured to different depths using additional mask sets (typically, a mask set per depth) using additional iterations of the FIG. 2C steps. Once the desired etch structures have been manufactured, one or more desired fill materials are blanket deposited 250 and the substrate surface 706 undergoes chemical mechanical planarization 256 (in a chemical mechanical planarization tool).
FIG. 2G shows an example of a prior art process for etching differentiated-profile structures that are then differently filled. As in the process shown in FIG. 2F, differentiated-profile etch structures can be manufactured using multiple masks in multiple iterations of the steps shown in FIG. 2C. Etch structures can then be differently filled using multiple masks in multiple iterations of the steps shown in FIG. 2D.
Process iterations required by the prior art processes shown in and described with respect to FIGS. 2F and 2G add concomitant overhead and defect susceptibility per iteration, corresponding to, for example, tool process cycles and tool transfers.
Ti represents the amount of time added by a corresponding process step. Yi represents the yield impact of a corresponding process step (one minus probability of introducing one or more yield-reducing defects). Where T is the total time taken by one or more material deposition, removal or modification processes, and Y is the expected yield following such material processes:
                    T        =                              ∑                          i              =              1                        N                    ⁢                      T            i                                              Equation        ⁢                                  ⁢        1                                Y        =                              ∏                          i              =              1                        N                    ⁢                                          ⁢                      Y            i                                              Equation        ⁢                                  ⁢        2            
Numerous steps in conventional semiconductor lithography material deposition, removal and modification processes are expensive and time consuming, and potentially introduce defects into the desired pattern, lowering yield. Process-induced defects can be introduced by, for example, wafer handling, resist spin and heating, lithography, resist development, etch, deposition, inspection, implantation, thermal processing, and chemical-mechanical polishing.